Center Concentrated X-Torus Topology

Dinesh Kumar, Vivek Kumar Sehgal, Nitin Nitin

Abstract


The topologies are the very important part of the interconnection network. The topologies once decided cannot be further modified in some cases, so we have to design best topology before its use. The regular topologies have been used in various massively parallel computers. In this paper, we have proposed a new variant of X-torus topology which the objective gets the better on the various qualities of service parameter like latency and throughput. The performance the proposed topology has been tested on the four traffic patterns and have been found that the topology is either better or same in the terms of performance. However, it has been found that we were able to get improvement of 85.24% in the terms of average latency than the other topologies similarly the throughput of the topology has improved by 17.86%. The Hop count is also another factor to study as if we can reduce the hop count in a particular topology we will be able to improve the performance and average hop count of our topology has been improved by 9.58%.

Keywords


Average Hop Count; Average Latency; Average Throughput; Interconnection Networks; Traffic Patterns;

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References


W. J. Dally and B. P. Towles, Principles and practices of interconnection networks. Elsevier, 2004.

R. Duncan, “Survey of parallel computer architectures,” Computer (Long. Beach. Calif)., vol. 23, pp. 5–16, 1990.

W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Design Automation Conference, 2001. Proceedings, 2001, pp. 684–689.

S. Yadav and C. R. Krishna, “CCTorus : A New Torus Topology for Interconnection Networks.”

L. K. Arora and Rajkumar, “C2Mesh,” in Advance Computing Conference (IACC), 2013 IEEE 3rd International, 2013, pp. 282–286.

W.-H. Hu et al., “Xmesh: a mesh-like topology for network on chip,” Netw. Chip Archit., p. 14.

L. Yu-hang, Z. Ming-fa, W. Jue, X. Li-min, and G. Tao, “Xtorus: An Extended Torus Topology for On-Chip Massive Data Communication,” in Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International, 2012, pp. 2061–2068.

Nitin, R. Vaish, and U. Shrivastava, “On a deadlock and performance analysis of ALBR and DAR algorithm on X-Torus topology by optimal utilization of Cross Links and minimal lookups,” J. Supercomput., vol. 59, no. 3, pp. 1252–1288, 2010.

A. Punhani and P. Kumar, “A Modified Diagonal Mesh Interconnection Network,” pp. 0–5.

W. Hu, S. Lee, and N. Bagherzadeh, “DMesh: a diagonally-linked mesh network-on-chip architecture,” First Int. Work. Netw. Chip Archit., pp. 1–7, 2008.

A. Chauhan, A. Punhani, and Nitin, “EMC2Mesh,” in 2015 Annual IEEE India Conference (INDICON), 2015, pp. 1–5.

A. Chauhan, A. Punhani, and Nitin, “Comparative analysis of traffic patterns on center connected topologies based on burton normal form,” in TENCON 2015-2015 IEEE Region 10 Conference, 2015, pp. 1–6.

A. Varga and others, “The OMNeT++ discrete event simulation system,” in Proceedings of the European simulation multiconference (ESM 2001), 2001, vol. 9, p. 65.

A. Chauhan, A. Punhani, and Nitin, “Comparative analysis of traffic patterns on center connected topologies based on burton normal form,” in IEEE Region 10 Annual International Conference, Proceedings/TENCON, 2016, vol. 2016–Janua.

Nitin and D. S. . Chauhan, “Comparative analysis of Traffic Patterns on k-ary n-tree using adaptive algorithms based on Burton Normal Form,” J. Supercomput., vol. 59, no. 2, pp. 569–588, 2012.

Sehgal,V.K., 2015. Markovian models based stochastic communication in networks-in-package. IEEE Transactions on Parallel and Distributed Systems, 26(10), pp.2806-2821.


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ISSN: 2180-1843

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