Development of a Wideband PLC Channel Emulator with Random Noise Scenarios

Ann Dulay, Ryan Sze, Aileen Tan, Roderick Yap, Lawrence Materum

Abstract


Channel emulators are an integral part of the test equipment that offers a more practical approach to testing new communication devices. It is imperative though to develop the emulator such that it best represents the channel. For PLC channel emulator, the channel representation can be either topdown or bottom-up. In this paper, the top-down characterisation and reference channels are used. In this approach, statistical measurements of the characteristics of the power line were conducted, and the closest mathematical representation is presented. The emulator operates in the frequency domain utilising 4096 transform points for the FFT process and 14 fractional bits for fixed point presentation. This number of bits allowed the emulator to sufficiently generate an average of 0.4% error between the software simulation results and the hardware test results. The input signal is converted to an LVDS signal by the FMC151 which serves as the AFE of the emulator. Two linear regulators block are used to convert both the negative and positive values of the input signal. The random generation of noise reduced the taxing efforts of adding different combinations of noise thus providing ease in focusing on the analysis of the resulting waveform.

Keywords


PLC; BBPLC; Emulator; Random Noise Generation; FPGA;

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References


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ISSN: 2180-1843

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