Design of High Performance Packet Classification Architecture for Communication Networks

Ausaf Umar Khan, Manish Chawhan, Yogesh Suryawanshi, Sandeep Kakde


Packet classification is a crucial technique for secure communication and networking. Security tools and internet services use packet classification technique which involves checking of packets against predefined rules stored in a classifier. The performance of the available software solutions of classification is not desirable and efficient for wire speed processing in high speed networks. Ternary Content Addressable Memory (TCAM), Bit-Vector (BV), field split bit vector (FSBV) and StrideBV algorithm are hardware based packet classification algorithms. In this paper, simple and memory efficient approach for packet classification has been proposed using Xnor gate instead of using lookup tables called XnorBV approach. Packet header fields of Internet protocol (IP) addresses and protocol layer are classified using Xnor gate against predefined ruleset which also support ternary bit pattern of ‘1’, ‘0’ and ‘*’ while port numbers of packet header support range match by comparing port numbers against lower bound and upper bound. The proposed parallel pipelined architecture can sustain a high throughput of +100 Gbps and low latency. The proposed method is memory efficient than other existing techniques, also supports prefix, range and exact match without use of range to prefix conversion. Also proposed XnorBV architecture is independent of ruleset feature and supports multiple dimension classification.


Firewall; Network Intrusion Detection System; Packet Classification; Quality Of Services;

Full Text:



Andrea Sanny, Thilan Ganegedara, Viktor K. Prasanna; “A Comparison of Ruleset Feature Independent Packet Classification Engines on FPGA,” in 27th International Symposium on Parallel & Distributed Processing Workshops and PhD Forum, 978-0-7695- 4979-8/13 $26.00 © 2013 IEEE.

T. Ganegedara and V. Prasanna, ‘‘StrideBV: 400G+ Single Chip Packet Classification,’’ in Proc. IEEE Conf. HPSR, 2012, pp. 1-6.

Mahmood Ahmadi, S. Arash Ostadzadeh, and Stephan Wong; “An Analysis of Rule-Set Databases in Packet Classification,” in 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands.

Nekoo Rafiei Karkvandi, Hassan Asgharian, Amir Kusedghi, Ahmad Akbari, “Hardware Network packet Classifier for High Speed Intrusion Systems,” in International Journal of Engineering and Technology; Volume 4 No.3, March, 2014.

Ausaf Umar Khan, Yogesh Suryawanshi, Dr. Manish Chawhan, Sandeep Kakde, “Design and Implementation of High performance Architecture for Packet Classification,” in International Conference on Advances in Computer Engineering and Applications, IMS Engineering College, Ghaziabad, India, page 598-602, IEEE.

Aladdin Abdulhassan and Mahmood Ahmadi, “Parallel Many Fields Packet Classification Technique using R-Tree ,” in Annual Conference on New Trends in Information & Communications Technology Applications-(NTICT'2017), 7-9 March 2017.

Safaa O.Al-Mamory and Wesam S.Bhaya; “Taxonomy of Packet Classification algorithms,” in Journal of Babylon University/Pure and Applied.

Balasaheb S. Agarkar and Uday V. Kulkarni, Ph.D., “A Novel Technique for Fast Parallel Packet Classification,” in International Journal of Computer Applications (0975 – 8887) Volume 76–No.4, August_2013.

Andreas Fiessler, Sven Hager and Björn Scheuermann, “Flexible Line Speed Network Packet Classification Using Hybrid On-chip Matching Circuits,” in IEEE 18th International Conference on High Performance Switching and Routing (HPSR), 18-21 June 2017.

Pankaj Gupta and Nick Mckneown; “Algorithms for packet classification,” in IEEE magazine, March/April 2001 pp. 24-32.

G. Jedhe, A. Ramamoorthy, and K. Varghese, ‘‘A Scalable High Throughput Firewall in FPGA,’’ in Proc. 16th Int’l Symp. FCCM. Apr. 2008, pp. 43-52.

Yeim-Kuan Chang and Cheng-Chien Su, “Efficient TCAM Encoding Scheme Packet Classification using Gray Code,” in IEEE GLOBECOM 2007 proceedings @2007 IEEE.

M. Faezipour and M. Nourani, ‘‘Wire-Speed TCAM-Based Architectures for Multimatch Packet Classification,’’ in IEEE Transactions on Computers, vol. 58, no. 1, pp. 5-17, Jan. 2009.

D.E. Taylor, ‘‘Survey and Taxonomy of Packet Classification Techniques,’’ in ACM Computing Survey, vol. 37, no. 3, pp. 238-275, Sept. 2005.

Lu Sun, Hoang Le, Viktor K. Prasanna; “Optimizing Decompositionbased Packet Classification Implementation on FPGAs,” in International Conference on Reconfigurable Computing and FPGAs; 978-0-7695-4551-6/11 $26.00 © 2011 IEEE; pp. 170-175.

W. Jiang and V. K. Prasanna, “Field-split Parallel Architecture for High Performance Multi match Packet Classification using FPGAs,” in Proc. of the21st Annual Symp. on Parallelism in Algorithms andArch. (SPAA), 2009, pp. 188–196.

Thilan Ganegedara, Weirong Jiang, and Viktor K. Prasanna, Fellow, IEEE; “A Scalable and Modular Architecture for High-Performance Packet Classification,” in IEEE Transactions On Parallel And Distributed Systems, Vol. 25, No. 5, May 2014; 1045-9219 _ 2013 IEEE, pp.1135-1144.

C.R. Meiners, A.X. Liu, and E. Torng, “Hardware Based Packet Classification for High Speed Internet Routers,” Berlin, Germany: Springer-Verlag, 2010.

Cheng-Liang Hsieh and Ning Weng, “Many-Field Packet Classification for Software-Defined Networking Switches,” in @ACM 2016 , ANCS ’16, March 17-18, 2016, Santa Clara, CA, USA.

H. Song and J.W. Lockwood, ‘‘Efficient Packet Classification for Network Intrusion Detection Using FPGA,’’ in Proc. ACM/SIGDA. 13th Int’l Symp. FPGA, 2005, pp. 238-245 .

Hung-Yi Chang, Chia-Tai Chan, Pi-Chung Wang, Chun-Liang Lee; “A Scalable Hardware Solution for Packet Classification,” in ICCS @2004 IEEE.

D. Taylor and J. Turner, ‘‘Scalable Packet Classification Using Distributed Crossproducing of Field Labels,’’ in Proc. 24th Annu. Joint IEEE INFOCOM, Mar.2005, vol.1, pp.269-280

C.A. Zerbini and J.M. Finochietto, ‘‘Performance Evaluation of Packet Classification on FPGA-Based TCAM Emulation Architectures,’’ in Proc. IEEE GLOBECOM, 2012, pp. 2766-2771.

Weirong Jiang and Viktor K. Prasanna, “Large-Scale Wire-Speed Packet Classification on FPGAs,” in ACM, 2009.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.

ISSN: 2180-1843

eISSN: 2289-8131